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september 2006 v 5 .0 1 ? 2006 actel corporation arinc 429 bus interface product summary intended use ? arinc 429 transmitter (tx) ? arinc 429 receiver (rx) key features ? supports arinc specification 429-16 ? configurable up to 16 rx and 16 tx channels ? programmable fifo depth ? up to 512 words ? programmable interrupt generation ? rx and tx channels independently ? up to 64 words ? configurable label memory size ? rx and tx channels independently ? up to 256 words ? internal, wrap-around testing ? software compatible with legacy devices ? selectable clock speed ? 1, 10, 16, or 20 mhz ? selectable data rate on each channel ? 12.5 100 kbps ? optional 50 kbps ? cpu interface ? provides direct cpu access to memory ? simple interface to core8051 ?memory ? edac support with rtax-s family ? arinc 429 bus interface ? supports standard line drivers and receivers ? available as integrated tx and rx supported families ?fusion ?proasic ? 3/e ?proasic plus ? ? axcelerator ? ?rtax-s core deliverables ? evaluation version ? compiled rtl simulation model, compliant with the actel libero ? integrated design environment (ide) ? netlist version ? structural vhdl and verilog netlists ? rtl version ? vhdl or verilog core source code ? synthesis scripts ? verification testbench ? verilog ? user testbenches ? libero ide compatible ? vhdl and verilog development system ? complete arinc 429 rx/tx ? implementation ? implemented in an apa600 device ? controlled via an external terminal using core8051 and rs232 links ? includes line driver and receiver components synthesis and simu lation support ? directly supported within the actel libero ide ? synthesis: ? synplicity? ? exemplar tm ? synopsys ? ? simulation ? vital-compliant vhdl simulators ? ovi-compliant verilog simulators verification and compliance ? actel-developed simulation testbench ? core implemented on the arinc 429 development system
arinc 429 bus interface 2 v5.0 general description core429 provides a complete transmitter (tx) and receiver (rx). a typical sy stem implementation using core429 is shown in figure 1 . the core consists of three main blocks: transmit, receive, and cpu interface ( figure 1 ). core429 requires connection to an external cpu. the cpu interface configures the transmit and receive control registers and initializes the label memory. the core interfaces to the arinc 429 bus through an ex ternal arinc 429 line driver and line receiver. a detailed description of the rx interface and tx interfac e is provided in the "functional description" section on page 5 . external components there are two external comp onents required for proper operation of core429: ? standard arinc 429 line driver ? standard arinc 429 line receiver arinc 429 overview arinc 429 is a two-wire, point -to-point data bus that is application-specific for commercial and transport aircraft. the connection wires are twisted pairs. words are 32 bits in length and mo st messages consist of a single data word. the specific ation defines the electrical standard and data characteristics and protocols. arinc 429 uses a unidirection al data bus standard (tx and rx are on separate po rts) known as the mark 33 digital information transfer system (dits). messages are transmitted at 12.5, 50 (opti onal), or 100 kbps to other system elements that are monitoring the bus messages. the transmitter is always tr ansmitting either 32-bit data words or the null state. the arinc standard supports high, low, and null states ( figure 2 ). a minimum of four null bits should be transmitted between arinc words. no more than 20 receivers can be connected to a single bus (wire pair) and no less than one receiver, though there will normally be more. figure 3 on page 3 shows the bit positions of arinc data. each arinc word contains five fields: ? parity contents general description .................................................... 2 arinc 429 overview .................................................. 2 core429 device requirements ................................... 3 memory requirements ............................................... 4 core429 overview ...................................................... 5 default mode ............................................................. 5 functional description ............................................... 5 legacy mode ............................................................... 7 core parameters ......................................................... 8 i/o signal descriptions ............................................... 8 default mode operation ......................................... 10 legacy operation ..................................................... 13 status register .......................................................... 15 cpu interface timing for default mode ................. 16 clock requirements .................................................. 17 core429 verification ................................................ 17 testbench .................................................................. 17 line drivers ............................................................... 18 line receivers ........................................................... 18 loopback interface ................................................... 18 development system ................................................ 18 ordering information .............................................. 19 list of changes ......................................................... 20 datasheet categories ............................................... 21 figure 1 ? typical core429 system?one tx and one rx figure 2 ? arinc standard actel fpga cpu glue logic coreARINC429 rx i/f tx i/f rxhi rxlo txhi txlo cpu interface 123456 7 8 910 32 1 1 1 1 1 1 0 0000 bit number "a" leg "b" leg data a b high null low +5 0 ?5 high null low +5 0 ?5
arinc 429 bus interface v5.0 3 ? sign/status matrix ?data ? source/destination identifiers ?label the parity bit is bit 32 (the msb). ssm is the sign/status matrix and is included as bits 30 and 31. bits 11 to 29 contain the data. binary coded decimal (bcd) and binary encoding (bnr) are common arinc data formats. data formats can also be mixed. bits 9 and 10 are source/ destination identifiers (sdi) and indicate for which receiver the data is intended. bits 1 to 8 contain a label (label words) identifying the data type. label words are quite specific in arinc 429. each aircraft may be equipped with diff erent electronic equipment and systems needing intercon nection. a large amount of equipment may be involved, depending on the aircraft. the arinc specification iden tifies the equipment id, a series of digital identification numbers. examples of equipment are flight management computers, inertial reference systems, fuel tanks, tire pressure monitoring systems, and gps sensors. transmission order the least significant bit of each byte, except the label, is tr ansmitted first, and the label is transmitted ahead of the data in each case. the order of the bits transmitted on the arin c bus is as follows: 8, 7, 6, 5, 4, 3, 2, 1, 9, 10, 11, 12, 13 ? 32. core429 device requirements core429 can be implemented in several actel fpga devices. table 1 through table 5 on page 4 provide typical utilization figures using standa rd synthesis tools for diff erent core429 c onfigurations. table 1 assumes that the label size is set to 64 and fifo depth is set to 64. figure 3 ? arinc data bit positions 32 31 11 10 9 label 30 29 1 8 lsb data pad discretes sdi p ssm msb table 1 ? device utilization for one tx module cells or tiles family combinatorial sequential tot al memory blocks device utilization fusion 363 147 510 1 afs600 4% proasic3/e 363 147 510 1 a3pe600 4% proasic plus 441 146 587 1 apa075 19% axcelerator 212 145 357 1 ax125 18% rtax-s 258 171 429 1 rtax250s 10% table 2 ? device utilization for one rx module cells or tiles family combinatorial seq uential total memory bl ocks devices utilization fusion 431 233 664 2 afs600 5% proasic3/e 431 233 664 2 a3pe600 5% proasic plus 588 236 824 2 apa075 27% axcelerator 307 234 541 2 ax125 27% rtax-s 350 259 609 2 rtax250s 14%
arinc 429 bus interface 4 v5.0 core429 clock rate can be programmed to be 1, 10, 16, or 20 mhz. all the actel families listed above easily meet the required performance. core429 i/o requirements depend on the system requirements and the external interfaces. if the core and memory blocks are implemen ted within the fpga and the cpu interface has a bidirectional data bus, then approximately 74 i/o pins ar e required to implement four rx and four tx modules. the core will require 62 pins to implement one rx and one tx module. the core has various fifo flags available for debugging purposes. these flag s may not be needed in the final design and this will reduce the i/o count. memory requirements the number of memory blocks required differs, depending on whether each channel is configured the same or differently. each channel configured the same use eq 1 to calculate the number of memory blocks required if each channel is configured the same. number of memory blocks = nrx * (int (label_size/x) + int (rx_fifo_depth/y) + ntx * int (fifo_depth/y), eq 1 table 3 ? device utilization for one rx and one tx module cells or tiles family combinatorial sequential tot al memory blocks device utilization fusion 848 609 1,457 3 afs600 10% proasic3/e 848 609 1,457 3 a3pe600 10% proasic plus 1,084 377 1,461 3 apa075 48% axcelerator 518 378 896 3 ax125 44% rtax-s 604 429 1,033 3 rtax250s 24% table 4 ? device utilization for 16 rx and 16 tx modules cells or tiles family combinatorial sequential total memory blocks device utilization fusion 13,435 9,614 23,049 48 afs1500 60% proasic3/e 13,435 9,614 23,049 48 a3pe1500 60% proasic plus 16,835 5,928 22,763 48 apa750 69% axcelerator 8,044 5,944 13,988 48 ax2000 43% rtax-s 9,594 6,745 16,339 48 rtax2000s 51% table 5 ? device utilization for lega cy mode (2 rx and 1 tx) family cells or tiles memory blocks device utilization combinational sequential total fusion 1,444 1,068 2,512 5 afs600 18% proasic3/e 1,444 1,068 2,512 5 a3pe600 18% proasic plus 1,840 674 2,514 5 apa150 41% axcelerator 955 653 1,608 5 rtax250s 20% rtax-s 1,062 729 1,791 5 rtax250s 42%
arinc 429 bus interface v5.0 5 where nrx is the number of receive chan nels, ntx is the number of transmit ch annels, int is the function to round up to the next integer, and x and y are defined in table 6 . each channel configured differently use eq 2 to calculate the number of memory blocks required if each channel is configured differently. number of memory blocks = int(fifo_depth[i]/y + (int(label_size[i]/x) + int(fifo_depth[i]/y)), eq 2 where nrx is the number of receive chan nels, ntx is the number of transmit ch annels, int is the function to round up to the next integer, and x and y are defined in table 6 . examples for the proasi c3/e device family if the design has 2 receivers, 1 transmitter, 64 labels for each receiver, 32-words-deep fifo for each receiver and transmitter, then the number of memory blocks = 2 * (int (64/512) + int (32/128)) + 1 * int (32/128) = 2 * (1 + 1) + 1 * (1) = 5. if the design has 2 receivers, 1 transmitter, 32 labels for rece iver # 1, 64 labels for receiver # 2, 32 words-deep fifo for receiver # 1, 64-words-deep fifo for receiver # 2, and 64-words-deep fifo for transmitter, then the number of memory blocks = int (64/128) + (int (32/512) + int (32/128)) + (int (64/512) + int (64/128)) = 1 + (1 + 1) + (1 + 1) = 5. core429 overview core429 provides a complete and flexible interface to a microprocessor and an ar inc 429 data bus. connection to an arinc 429 data bus requires additional line drivers and line receivers. core429 interfaces to a proces sor through the internal memory of the receiver. core429 can be easily interfaced to an 8-, 16- or 32-bit data bus. look-up tables loaded into memory enable the core429 receive circuitry to filter and sort incoming data by label and destination bits. core429 supports multiple (c onfigurable) arinc 429 receiver channels, and each receives data independently. the receiver data rates (high or low speed) can be programmed independently. core429 can decode and sort data based on the arinc 429 label and sdi bits and stores it in fifo. each receiver uses programmable fifo to buffer received data. core429 supports multiple (configurable) arinc 429 tr ansmit channels and each channel can transmit data independently. default mode this is the recommended mo de and allows the user to configure the core with user-defined transmit and receive channels. functional description the core has three main blocks: transmit, receive, and cpu interface. the core can be configured to provide up to 16 transmit and receive channels. table 6 ? memory parameters device family x y fusion 512 128 proasic3/e 512 128 proasic plus 256 64 axcelerator/rtax-s 512 128 i0 = ntx 1 ? i0 = nrx 1 ?
arinc 429 bus interface 6 v5.0 figure 4 gives a functional description of the rx block. the rx block is responsible for recovering the clock from the input serial data and performs serial-to-parallel conversion and gap/parity check on the incoming data. it also interfaces with the cpu. the rx module contains two 8-bit registers. one is used for control function and the other is used for status. refer to table 14 on page 11 and table 15 on page 11 for detailed descriptions of the control and status register bits. the cpu interf ace configures the internal ram with the labels, which ar e used to co mpare against the incoming labels from the received arinc data. if the label-compare bit in th e receive control register is enabled, then the data which matches its labels with the stored labels will be stored in the fifo. if the label- compare bit in the receive co ntrol register is disabled, then the incoming data will be stored in the fifo without comparing against the labels in ram. the core supports reloading label memory using bit 7 of the rx control register. note that when you set bit 7 to initialize the label memory, the old label content still exists, but the core keeps track only of the new label and does not use the old label during label compare. the fifo asserts three status signals: ? rx_fifo_empty: fifo is empty ? rx_fifo_half_full: fifo is filled up to the programmed rx_fifo_level ? rx_fifo_full: fifo is full depending on the fifo status signals, the cpu will either read the fifo before it overflows, or not attempt to read the fifo if it is empty. th e interrupt signal int_out_rx is generated when one of the fifo status signals (rx_fifo_empty, rx_fifo_half _full, and rx_fifo_full) are high. figure 4 ? core429 rx block diagram data sync and clock recovery 32-bit shift register label memory bit counter word gap timer parity check control logic control reg status reg cpu i/f compare label fifo rxlo rxhi clk cpu_add cpu_wen cpu_ren cpu_din cpu_dout cpu_wait
arinc 429 bus interface v5.0 7 figure 5 gives a functional description of the tx block. the tx module converts the 32-bit parallel data from the tx fifo to serial data. it also inserts the parity bit into the arinc data when parity is enabled. the cpu interface is used to fill the fifo with arinc data. the tx fifo can hold up to 512 arinc words of data. the transmission starts as soon as one complete arinc word has been stored in the transmit fifo. the tx module contains two 8-bit registers. one is used for a control function and the other is used for status. the cpu interface allows the system cpu to access the control and status registers within the core. the tx fifo asserts three status signals: ? tx_fifo_empty: tx fifo is empty ? tx_fifo_half_full: tx fifo is filled up to the programmed tx_fifo_level ? tx_fifo_full: tx fifo is full depending on the fifo status signals, the cpu will either read the fifo before it overflows, or not attempt to read the fifo if it is empty. th e interrupt signal int_out_tx is generated when one of the fifo status signals (tx_fifo_empty, tx_fifo_half _full and tx_fifo_full) are high. legacy mode in this mode, there is a legacy interface block that communicates with the cp u interface. when legacy mode is enabled, the core supports two receive (rx) channels and one transmit (tx) channel only. this is not configurable. figure 5 ? core429 tx block diagram 32-bit parallel- to-serial register control logic control reg status reg cpu i/f parity generator fifo clk cpu_add cpu_wen cpu_ren cpu_din cpu_dout cpu_wait waveform shaper rxlo rxhi load shift
arinc 429 bus interface 8 v5.0 core parameters core429 has several top-level verilog parameters (vhdl generics) that are used to se lect the number of channels and fifo sizes of the core that is implemented. using these parameters allows the size of the core to be reduced when all the cha nnels are not required. for rtl versions, the parameters in table 7 can be directly set. for netlist vers ions of the core, a netlist implementing four tx and four rx channels is provided as per the defaults above. actel will supply netlists with alternative parameter settings on request. i/o signal descriptions arinc interface table 7 ? fifo and label parameters parameter name description allowed values default clk_freq clock frequency 1, 10, 16, 20 mhz 1 mhz cpu_data_width cpu data bus width 8, 16, 32 bits 8 rxn rx channels 1 to 16 4 txn tx channels 1 to 16 4 legacy_mode 0 = normal mode; 1 = legacy mode 0,1 0 label_size_i number of labels for rx channel i 1 to 256 64 rx_fifo_depth_j depth of fifo for rx chan nel j arinc word 32, 64, 128, 25 6, 512 32 rx_fifo_level_k fifo level fo r rx channel k 1 to 64 16 tx_fifo_depth_l depth of fifo for tx channel l arinc word 32, 64, 128, 256, 512 32 tx_fifo_level_m fifo level fo r tx channel m 1 to 64 16 txrxspeed_n when this parameter is set to '1', a bit rate of 100/50 kbps is selected. otherwise selects a bit rate of 100/12.5 kbps. the bit rate can be changed for the rx/tx channel pair. refer to the tx and rx control register bit descriptions in table 14 on page 11 and table 18 on page 12 . 0, 1 0 note: where i, j, k, l, m, and n are from 0 to 15. table 8 ? clock and reset name type description clk in master clock input (1, 10, 16, or 20 mhz) reset_n in active low asynchronous reset txa [txn-1:0] out arinc transmit output a txb [txn-1:0] out arinc transmit output b rxa [rxn-1:0] in arinc receiver input a rxb [rxn-1:0] in arinc receiver input b
arinc 429 bus interface v5.0 9 default mode signals cpu interface the cpu interface allows access to th e core429 internal registers, fifo, a nd internal memory. this interface is synchronous to the clock. table 9 ? core interface signals name type description int_out_rx[rxn-1:0] out interrupt fr om each receive channel. this interrupt is generated when one of the following conditions occur: ? fifo empty ? fifo full ? fifo is full up to the programmed rx_fifo_level this is an active high signal. int_out_tx[txn-1:0] out interrupt from each transmit channel. this interrupt is generated when one of the following conditions occur: ? fifo empty ? fifo full ? fifo is full up to the programmed tx_fifo_level this is an active high signal. rx_fifo_full[rxn-1:0] out rx fifo fu ll flag for each receive channel. this is an active high signal. rx_fifo_half_full[rxn-1:0] out rx fifo programmed level flag for each receive channel. by default it is programmed to half full. this is an active high signal. rx_fifo_empty[rxn-1:0] out rx fifo empty flag for each receive channel.this is an active high signal. tx_fifo_full[txn-1:0] out tx fifo fu ll flag for each transmit channel. this is an active high signal. tx_fifo_half_full[txn-1:0] out tx fifo programmed level flag for each transmit channel. by default it is programmed to half full. this is an active high signal. tx_fifo_empty[txn-1:0] out tx fifo empty flag for each transmit channe l. this is an active high signal. table 10 ? cpu interface signals name type description cpu_ren in cpu read enable, active low cpu_wen in cpu write enable, active low cpu_add [8:0] in cpu address cpu_din [cpu_data_width-1:0] in cpu data input cpu_dout [cpu_data_width-1:0] out cpu data output int_out out interrupt to cpu, active high. int_out is the or function of int_out_rx and int_out_tx. cpu_wait out indicates that the cpu should hold cpu_ren or cpu_wen active while the core comp letes the read or write operation.
arinc 429 bus interface 10 v5.0 legacy interface the legacy interface allows access to the core429 internal registers, fifo, and intern al memory. this interface is synchronous to the clock. the tx module contains two 8-bit registers. one is used for control function and the other is used for status. default mode operation in the default mode, the core operates with the following register map. cpu address map the address bits 0 and 1 are used to create byte indexes. for an 8-bit cpu data bus: 00 ? byte 0 01 ? byte 1 10 ? byte 2 11 ? byte 3 for a 16-bit cpu data bus: 00 ? lower half word 10 ? upper half word for 32-bit cpu data bus: 00 ? word the address bits 2 and 3 select the registers within each rx or tx block (see "address map" on page 11 ). table 11 ? legacy interface signals name type description data_ready1 out receiver 1 data ready (fifo not empty) flag fifo_full1 out recei ver 1 fifo full half_full1 out receiver 1 fifo half full data_ready2 out receiver 2 data ready (fifo not empty) flag fifo_full2 out recei ver 2 fifo full half_full2 out receiver 2 fifo half full transmit_fifo_full out transmit fifo full transmit_half_full out transmit fifo half full rsel in receiver data half word selection ctrl_n in clock for control word register str_n in read status register if rsel = 0, read control register if rsel = 1 entx in enable transmission txr out transmitter ready flag. go es low when arinc word loaded into fifo. goes high after transmission and fifo empty. pl1_n in latch enable for word 1 entere d from data bus to transmitter fifo pl2_n in latch enable for word 2 entered from da ta bus to transmitter fifo. must follow pl1_n. en1_n in data bus control, enables receiver 1 data to outputs en2_n in data bus control, enables receiver 2 data to outputs if en1_n is high test in disable transmitter output if high dout in/out bidirectional data bus data_valid out data is valid when data_valid = 1
arinc 429 bus interface v5.0 11 the address bit 4 is used to determine rx/tx as follows: 0 ? rx 1 ? tx the address bits 5, 6, 7, a nd 8 are used for decoding the 16 channels as follows: 0000 ? channel0 0001 ? channel1 . . . . 1110 ? channel14 1111 ? channel15 table 12 shows the cpu address bit information. register definitions rx registers following is the detailed definition of cpu_add [3:2] decoding and the explanation of data register, control register, status register, and label memory register ( table 13 through table 16 on page 12 ). address map 00 ? data register 01 ? control register 10 ? status register 11 ? label memory table 12 ? cpu address bit positions channel number tx/rx register index byte index 876543210 msb 9-bit cpu address lsb table 13 ? rx data register bit function reset state type description 31:0 data 0 r read data table 14 ? rx control register bit function reset state type description 0 data rate 0 r/w data rate: 0 = 100kb/s; 1 = 12.5 or 50 kbps 1 label recognition 0 r/w label compare: 0 = disable; 1 = enable 2 enable 32 nd bit as parity 0 r/w 0 = 32 nd bit is data; 1 = 32 nd bit is parity 3 parity 0 r/w parity: 0 = odd; 1 = even 4 decoder 0 r/w 0: sdi bit comparison disabled; 1: sdi bit comparison enabled; arinc bits 9 and 10 must match bits 5 and 6 respectively. 5 match header bit 9 0 r/w if bit 4 is set th en this bit should match the arinc header bit 9 (sdi bit). 6 match header bit 10 0 r/w if bit 4 is set th en this bit should match the arinc header bit 10 (sdi bit). 7 reload label memory 0 r/w when bit 7 is set to '1', label memory address pointers are initialized to '000'. set this bit to change the contents of the label memory. table 15 ? rx status register bit function reset state type description 0 fifo empty 0 r 0 = not empty; 1 = empty 1 fifo half full or programmed level 0 r 0 = less than programmed level; 1 = fifo is filled at least up to programmed level 2 fifo full 0 r 0 = not full; 1 = full
arinc 429 bus interface 12 v5.0 tx registers following is a detailed definition of cpu_add [3:2] decoding and an explanatio n of the data register, pattern ram, control register, and status register. address map 00 ? data register 01 ? control register 10 ? status register 11 ? unused table 16 ? rx label memory register bit function reset state type description 7:0 label 0 r/w read/write labels table 17 ? tx data register bit function reset state type description 31:0 data 0 w write data table 18 ? tx control register bit function reset state type description 0 data rate 0 r/w data rate: 0 = 100kb/s; 1 = 12.5 or 50 kbps 1 loopback 0 r/w 0 = disable loopback; 1 = enable loopback 2 enable 32 nd bit as parity 0 r/w 0 = 32 nd bit is data; 1 = 32 nd bit is parity 3 parity 0 r/w parity: 0 = odd; 1 = even table 19 ? tx status register bit function reset state type description 0 fifo empty 0 r 0 = not empty; 1 = empty 1 fifo half full or programmed level 0 r 0 = less than half full or programmed level; 1 = half full or programmed level 2 fifo full 0 r 0 = not full; 1 = full
arinc 429 bus interface v5.0 13 label memory operation the label memory is impl emented using an internal memory block. the read ad dress and write address are generated by internal counters. the read and write address counters can be reset by setting bit 7 of the receive (rx) control register to '1'. the write counter increments each time the label memory register is written. the read counter increments every time the label memory register is read. the label memory operation is shown in figure 6 . to program labels, the cpu first resets the read and write counters by setting bit 7 of the receive (rx) control register to '1'. then the la bels are written to the label memory. the core will compare the incoming arinc word label (bit 1 to 8 of arinc word) against the labels contained in the label memory . the contents of the label memory can be read by reading the label memory register. while writing to or reading from label memory, bit 1 of the receive (rx) control register should be set to '0'. to reload the label memory, set bit 7 of the receive (rx) control register to '1'. the core will then ignore all previous labels and new labe ls can be written to the label memory. legacy operation in this mode, there is a legacy interface block that communicates with the cp u interface. when legacy mode is enabled, the core supports two receive (rx) channels and one transmit (tx) channel only. legacy mode is not configurable to support multiple transmit and receive channels. the pu rpose of the legacy mode interface is to replace ex isting standard products. figure 6 ? label memory diagram read address counter write address counter label memory block +1 +1 rx control register bit rx control register bit write data (rx label memory register) read data (rx label memory register) number of active labels wdata rdata raddr waddr reset reset write enable read enable label enable
arinc 429 bus interface 14 v5.0 control register core429 contains a 16-bit control register , which is used to configure the rx an d tx channels. the control register bits 0 to 15 are loaded from the databus when ctrl_n is low. the control register contents are output on the databus when rsel is high and str_n is low. each bit of the control register description is explained in table 20 . table 20 ? legacy control register bit function reset state type description 0 receiver 1 data rate 0 r/w data rate: 0 = 100 kbps; 1 = 12.5 kbps. note: does not support 50 kbps. 1 label compare 0 r/w 0 = disable; 1 = enable load 16 labels using pl1_n/pl2_n read 16 labels using en1_n/en2_n 2 enable label recognition (receiver 1) 0 r/w 0: disable label recognition 1: enable label recognition 3 enable label recognition (receiver 2) 0 r/w 0: disable label recognition 1: enable label recognition 4 enable 32 bit as parity 0 r/w 0 = 32 bit is data; 1 = 32 bit is parity 5 self test 1 r/w 0: the transmitter?s digital outputs are internally connected to the receiver logic inputs. 1: normal operation 6 receiver 1 decoder 0 r/w 0: receiver 1 decoder disabled 1: arinc bits 9 and 10 must match bits 7 and 8 of the control register. 7 match arinc bit 9 (receiver 1) 0 r/w if receiver 1 decoder is enabled, the arinc bit 9 should match this bit. 8 match arinc bit 10 (receiver 1) 0 r/w if receiver 1 decoder is enabled, the arinc bit 10 should match this bit. 9 receiver 2 decoder 0 r/w 0: receiver 2 decoder disabled 1: arinc bits 9 and 10 must match bits 10 and 11 of the control register. 10 match arinc bit 9 (receiver 2) 0 r/w if receiver 2 decoder is enabled, the arinc bit 9 should match this bit. 11 match arinc bit 10 (receiver 2) 0 r/w if receiver 2 decoder is enabled, the arinc bit 10 should match this bit. 12 transmitter parity 0 r/w parity: 0 = odd; 1 = even 13 transmitter data rate 0 r/w data rate: 0 = 100 kbps; 1 = 12.5 kbps. note: does not support 50 kbps. 14 receiver 2 data rate 0 r/w data rate: 0 = 100 kbps; 1 = 12.5 kbps. note: does not support 50 kbps.
arinc 429 bus interface v5.0 15 status register core429 contains a 16-bit status register which can be read to determine th e status of the arinc receivers, data fifos, and transmitter. the contents of the sta tus register are output on the databus wh en rsel is low and str is low. each bit of the control register description is explained in table 21 . table 21 ? legacy status register bit function reset state type description 0 receiver 1 fifo empty 0 r 0 = receiver 1 fifo not empty 1 = receiver 1 fifo empty 1 receiver 1 fifo half full 0 r 0 = receiver 1 fifo not half full 1 = receiver 1 fifo half full 2 receiver 1 fifo full 0 r 0 = receiver 1 fifo not full 1 = receiver 1 fifo full 3 receiver 2 fifo empty 0 r 0 = receiver 2 fifo not empty 1 = receiver 2 fifo empty 4 receiver 2 fifo half full 0 r 0 = receiver 2 fifo not half full 1 = receiver 2 fifo half full 5 receiver 2 fifo full 0 r 0 = receiver 2 fifo not full 1 = receiver 2 fifo full 6 transmitter fifo empty 0 r 0 = transmitter fifo not empty 1 = transmitter fifo empty 7 transmitter fifo full 0 r 0 = transmitter fifo not full 1 = transmitter fifo full 8 transmitter fifo half full 0 r 0 = transmitter fifo not half full 1 = transmitter fifo half full
arinc 429 bus interface 16 v5.0 cpu interface timing for default mode the cpu interface signals are synchr onized to the core429 master clock. figure 7 through figure 12 on page 17 show the waveforms for the cpu interface. note: cpu_ren should be deasserted on the next cl ock cycle after cpu_wait is deasserted. th e read data is available one cycle after c pu_ren is sampled. figure 7 ? cpu interface control/status register read cycle note: cpu_wen should be deasserted on the next clock cycle after cpu_wait is deasserted. th e write is done two cycles after cpu_wen i s sampled. figure 8 ? cpu interface control register write cycle note: cpu_ren should be deasserted on the next clock cycle after cpu_wait is deasserted. the read data is available six cycles after cpu_ren is sampled. figure 9 ? cpu interface data register read cycle note: cpu_wen should be deasserted on the next clock cycle after cpu_wait is deasserted. the write is done two cycles after cpu_wen is sampled. figure 10 ? cpu interface data register write cycle clk cpu_ren cpu_add[8:0] cpu_dout[31:0] addr data cpu_wait clk cpu_wen cpu_add[8:0] cpu_din[31:0] addr write done cpu_wait clk cpu_ren cpu_add[8:0] cpu_dout[31:0] addr data cpu_wait clk cpu_wen cpu_add[8:0] cpu_din[31:0] addr data write cpu_wait
arinc 429 bus interface v5.0 17 clock requirements to meet the arinc 429 transmission bit rate requirements, the core429 clock input must be 1, 10, 16, or 20 mhz with a tolerance of 0.01%. core429 verification the comprehensive verification simulation testbench (included with the netlist and rtl versions of the core) verifies correct operation of the core429 macro. the verification testbench applies several tests to the core429 macro, including: ? receive interface tests ? transmit interface tests ? cpu interface tests ? legacy interface tests ? loopback tests using the supplied user testbench as a guide, the user can easily customize the verification of the core by adding or removing tests. testbench the cpu model sets up core429 via the cpu interface and loads the transmit data . the transmit data will be sent to the receiver. the cpu model can retrieve the receive data through the cp u interface and compare it against the transmitted data. the core comes with three testbenches: a full verification testbench that demonstrates full operation in verilog, and two user testbenches, one in vhdl and the other in verilog. the user testbenches are intended to simplify core integration into the target system ( figure 13 ). this consists of the core connections to a cpu model and loopback logic that connects tx output to the rx input. note: cpu_ren should be deasserted on the next cl ock cycle after cpu_wait is de asserted. the read data is available six cycles after cpu_ren is sampled. figure 11 ? cpu interface label memory read cycle note: cpu_wen should be deasserted on the next clock cycle after cpu_wait is deasserted. th e write is done two cycles after cpu_wen i s sampled. figure 12 ? cpu interface label memory write cycle clk cpu_ren cpu_add[8:0] cpu_dout cpu_wait data clk cpu_wen cpu_add[8:0] cpu_din[31:0] addr data write cpu_wait figure 13 ? testbench diagram cpu model loopback i/f cpu i/f rx i/f0 tx i/f0 rx i/f3 tx i/f3 rxh0 rxl0 txh0 txl0 rxh3 rxl3 txh3 txl3 core429
arinc 429 bus interface 18 v5.0 line drivers core429 needs arinc 429 line drivers to drive the arinc 429 data bus. core429 is designed to directly interface to common arinc 429 line drivers, such as the holt hi-8382/hi-8383, ddc dd -03182 or device engineering dei1070. figure 14 shows the connections required from core429 to the line drivers. line receivers core429 needs arinc 429 line receivers to receive the arinc 429 data bus. core429 is designed to directly interface to common arinc 429 line receivers, such as the holt hi-8588 or device engineering dei3283. when using proasic plus , rtax-s, or axcelerator fpga families, level translators are require d to connect the 5 v output levels of the core429 line receivers to the 3.3 v input levels of the fpga. figure 15 on page 19 shows the connections required from core429 to the line receivers. loopback interface if the loopback bit in the transmit control register is enabled, the transmit output s will be connected to the receive inputs. if there ar e equal numbers of transmit and receive channels, each transmit channel output is connected to the correspondi ng receive channel input. as an example, transmit ch annel 0 output is connected to receive channel 0 input. if there are more receiv e channels than transmit channels, then the extra re ceive channels are connected to transmit channel 0. as an example, if we have two transmit channels (0 and 1) an d four receive channels (0, 1, 2, and 3) then the connections are made as follows: ? connect transmit channel 0 output to receive channel 0 inputs. ? connect transmit channel 1 output to receive channel 1 input. ? connect transmit channel 0 output to receive channel 2 input. ? connect transmit channel 0 output to receive channel 3 input. development system a complete arinc 429 development system is also available, actel part number "core429-dev-kit". the development system uses an ex ternal terminal (pc) using a serial uart link to contro l core429 with four rx and four tx channels implemented in a single proasic plus apa600 fpga. the loopback interface logi c allows the arinc core to operate with the loopback mode. the development kit ( figure 15 on page 19 ) includes arinc line drivers and line receivers. on power-up, core8051 will read the message from the adc, which could be the aircraft fuel level or flap position, for example, and transmits over the transmit channel. the message will be transmitted to the receiver through the loopback interf ace. then the message will be retrieved by core8051 from the receiver and displayed on the lcd display. another way is to transmit the adc message over the transmit channel through th e line drivers to another system similar to the one described above. the message will go through the receive channel of the second system and can be displayed on the lcd display. figure 14 ? core429 line driver and line receiver interface coreARINC429 rx i/f tx i/f rxhi rxlo txhi txlo line driver line receiver cpu interface
arinc 429 bus interface v5.0 19 ordering information core429 can be ordered through your local actel sales representative. it should be ordered using the following part number: core429-xx, where xx is the appropriate value from table 22 : the evaluation board can also be ordered using the part number "core429-dev-kit". figure 15 ? typical core429 system diagram table 22 ? ordering codes xx description ev evaluation version sn netlist for single use on actel devices an netlist for unlimited use on actel devices sr rtl for single use on actel devices ar rtl for unlimited use on actel devices ur rtl for use not restricted to actel devices apa600 fpga core 8051 core 429 4tx and 4tx loop- back i/f uart rs232 keypad and lcd display terminal adc tx1h tx1l rx1h rx1l tx2h tx2l rx2h rx2l tx3h tx3l rx3h rx3l tx4h tx4l rx4h rx4l
arinc 429 bus interface 20 v5.0 list of changes the following table lists critical changes that were made in the current version of the document. previous version changes in current version (v 5 .0 ) page v4.1 the "key features" section was updated to modify the select able data rate on each channel. 1 figure 2 was added. 2 the "general description" section and "arinc 429 overview" section were updated. 2 a paragraph was added to the end of the "core429 device requirements" section . 3 ta b l e 6 was updated to add fusion. 5 figure 3 was updated. 3 the "default mode" section was added. 5 the "functional description" section was updated. 5 the "legacy mode" section was added. 7 ta b l e 7 was updated to add the txrxspeed_n parameter, and the table note was updated. 8 the first four rows of ta b l e 9 were moved to ta b l e 8 . ta b l e 9 was updated to remove the tx_en signal, modify the int_out_tx signal description, and add the rx_fifo_full through tx_fifo_empty signals. the "clock and reset" section was renamed to "arinc interface" and the "arinc interface" section was renamed to "default mode signals" . 8 ? 9 ta b l e 1 1 was moved to a later position in the document, just before the "default mode" section . 10 information about the tx module was added to the "legacy interface" section . 10 the channel decoding values were updated for the 32-bit cpu data bus in the "default mode operation" section . 10 the address map was updated in the "rx registers" section and the "tx registers" section . 11 , 12 ta b l e 1 4 was updated to modify the data rate, decode r, match header bit 9, and match header bit 10 descriptions. label memory address was rename d reload label memory, and its description was updated. 11 ta b l e 1 5 was updated to rename fifo half full to fi fo half full or programmed level, and the description was modified. 11 ta b l e 1 6 was updated to rename data to label and update the type and description. 12 ta b l e 1 8 was updated to modify the data rate description. 12 ta b l e 1 9 was updated to modify the type of fifo empty and fifo full. fifo half full was renamed to fifo half full or programmed level, and its type and description were modified. 12 the "label memory operation" section was added. 13 information was added to the "legacy operation" section to clarify its purpose and configurability. 13 ta b l e 2 0 was updated to modify the de scription for receiver 1 data rate, label compare, match arinc bit 10, match arinc bit 9, transmitte r data rate, and transmitter data rate. 14 ta b l e 2 1 was updated to change the type from r/w to r for all bits. 15 the signal names cpu_clk and cpu_addr[7:0] were changed to clk and cpu_add[8:0] in figure 7 through figure 12 . the wave forms were modified in figure 7 , figure 10 , figure 11 , and figure 12 , and notes were added to each figure. 16 ? 17
arinc 429 bus interface v5.0 21 datasheet categories in order to provide the latest information to designers, some datasheets are published before data has been fully characterized. datasheets are designated as "product brief," "advanced," and "production." the definitions of these categories are as follows: product brief the product brief is a summarized version of an advanced or production datasheet containing general product information. this brief summarizes specific devi ce and family information for unreleased products. advanced this datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. this information can be used as estimates, but not for production. unmarked (production) this datasheet version contains informat ion that is considered to be final. v4.0 the title of ta b l e 4 was updated. the fusion device was changed to afs1500. 4 v3.1 the "supported families" section was updated to include fusion. 1 the "core429 device requirements" section was updated to include fusion data. 3 v3.0 the "core deliverables" section was updated. 1 ta b l e 5 is new. 4 ta b l e 9 was updated. 9 figure 9 was updated. 16 v2.0 the "core429 device requirements" section was updated. 3 ta b l e 1 was updated. 3 ta b l e 2 was updated. 3 ta b l e 3 was updated. 4 ta b l e 4 was updated. 4 ta b l e 2 0 was updated. 14
51700055-5/9.06 actel corporation 2061 stierlin court mountain view, ca 94043-4655 usa phone 650.318.4200 fax 650.318.4600 actel europe ltd. dunlop house, riverside way camberley, surrey gu15 3yl united kingdom phone +44 (0) 1276 401 450 fax +44 (0) 1276 401 490 actel japan www.jp.actel.com exos ebisu bldg. 4f 1-24-14 ebisu shibuya-ku tokyo 150 japan phone +81.03.3445.7671 fax +81.03.3445.7668 actel hong kong www.actel.com.cn suite 2114, two pacific place 88 queensway, admiralty hong kong phone +852 2185 6460 fax +852 2185 6488 www.actel.com actel and the actel logo are registered trademarks of actel corporation. all other trademarks are the property of their owners.

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